Conventional systems may use server computers or storage devices that are arranged on blades or motherboards within a rack. The backplane of the rack has power and data connections, where the focus of this discussion is on power. The motherboard or blade has power connectors that physically interface with the power connections on the backplane of the rack, thereby providing power to the components on the motherboard or blade. In one example, 230V AC power is converted to 12V DC power and provided to the backplane. The motherboard or blade receives the 12V DC and, if needed, may perform further power conversion internally.
Furthermore, some conventional systems require high availability and are not usually turned off even for adding/removing a component from the rack. For instance, some storage systems that have multiple motherboards interfacing with a backplane provide for a technique called “hot swapping,” where a motherboard can be added and/or removed from a rack without powering off the rack. However, in the case of adding a motherboard to a powered rack, the motherboard may experience inrush current. In some instances, inrush current is caused when the uncharged capacitors on a motherboard draw current the instant the motherboard is plugged into the power bus. As the capacitors become charged, the inrush current decreases to zero. It should be noted that inrush current is in addition to any operating current being drawn into the motherboard, so that the total instantaneous current can be quite high and may cause damage to the circuits and/or cause a circuit breaker or fuse to break the circuit.
Various solutions have been proposed for handling inrush current. One conventional solution uses Field Effect Transistors (FETs) in the current path to supply power for the inrush current. A conventional inrush FET causes a voltage drop in series with the power delivering path (even during steady state, after the initial inrush is over). Furthermore, it is desirable that an inrush FET be able to withstand large instantaneous power surge when operating in its linear region during turn-on. Therefore, in many instances, it would be desirable to have an inrush FET with a low on-resistance (or Rdson, the resistance in steady state operation) and a wide Safe Operating Area (SOA, a limit of instantaneous power). The dilemma is that an FET with a wide SOA is usually large in size and does not necessarily have a low on-resistance, and an FET with a low on-resistance is usually small in size and with a narrow SOA. Hence, system designers have in the past placed several large FETs in parallel to guarantee a small voltage drop for the circuit during steady state and a large SOA for each of the individual FETs, but at the cost of a large foot print for the circuit.
In one example, a conventional system places multiple, large FETs in parallel with respect to each other within the current path of a motherboard. When the motherboard is placed in a rack and interfaced with a hot power bus, the inrush current begins. The multiple, large FETs all begin conducting at the same time in their linear regions, supplying the inrush current and generating heat energy from the inrush current. After a certain time, the multiple, large FETs leave their linear regions and enter their ON states for steady state operation of the motherboard. The on-resistance for an individual FET is less than the apparent resistance for the same FET during linear region operation. Also, the parallel arrangement of the FETs provides a total resistance that is lower than that of any one of the individual FETs. Thus, the current path of the motherboard, during steady state operation, is not impeded by the resistance of the parallel FETs. While such a solution operates well enough for some applications, the multiple, large FETs may take up an undesirably large amount of space on the motherboard. Thus, such a solution may be space-inefficient.